One of my specialities is Emulation of Silicon chips using FPGAs.  I have designed some of the most complex emulation systems in the industry.   I have created systems that have done a full chip emulation utilizing up to 11 FPGAs in one platform.   I can help you whether you are   designing your own board or are using an off the shelf platform.

Some things that I have learned over the years.

1. -Any emulation project is ultimately limited by two things, the number of pins required to interconnect blocks and the total gates required to emulate the design.
   

2. -Start by partitioning the design into multiple fpgas based on size and pins.
   

3. -Estimate these pins and gates early on and track them throughout the design as it changes
   

4. -Avoid debugging on the board when possible.  Do debug in simulation.
   

5. -Error check the pin location constraints, preferably in the simulation environment using the board file if possible.
   

6. -Replace gated clocks.  Most synthesis tools do not do a very good job at utilizing the CE function in the fpga and it often leads to problems that are difficult to debug.
   

7. -Customize cells that do not port well to fpgas, i.e. SDRAM front ends, TLBs, async blocks.

Time division multiplexing:  I have cells that have 2x tdm that runs up to 33Mhz and a 4x that runs up to 10Mhz while retaining full cycle accuracy.  This has the advantage of being transparent to the design.

Bus Sharing:  Multiple devices can be shared on a single bus and tristated when not in use provided that both devices do not need to access memory at the same time.

Serialization:  This a technique where configuration registers are loaded over multiple clock cycles and stalled while the register is loaded.

Contact me at mrally@extremedesignsonline.com to discuss your emulation project

How to save pins on a design

This is almost always Pins required to interconnect block are limited by the pins on the fpga chips themselves.  The largest pin count FPGAs have no more than about 1000-1200 pins available depending on the device.  There is usually a pin constraint usually occur at the memory interface as multiple devices try to access the controller or involving configuration registers

This constraint can be reduced by the use of several techniques where applicable.